FIN field effect transistor with self-aligned gate

ABSTRACT

The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor devices, and moreparticularly to a method of forming a metal oxide semiconductor fieldeffect transistor (MOSFET) comprising thin vertical channels (i.e., theFIN) controlled by a double-gate, which involves using a trough todefine the channel regions as well as the damascene gate, so as toprovide a self-aligned gate. The present invention also relates to asub-0.05 μm double-gated/double-channel FIN MOSFET structure wherein thegate is self-aligned to the channel regions as well as the source/drainjunctions.

BACKGROUND OF THE INVENTION

[0002] Over the past twenty-five years or so, the primary challenge ofvery large scale integration (VLSI) has been the integration of anever-increasing number of MOSFET devices with high yield andreliability. This was achieved mainly in the prior art by scaling downthe MOSFET channel length without excessive short-channel effects. As isknown to those skilled in the art, short-channel effects are thedecrease of threshold voltage Vt in short-channel devices due totwo-dimensional electrostatic charge sharing between the gate and thesource/drain diffusion regions.

[0003] To scale down MOSFET channel lengths without excessiveshort-channel effects, gate oxide thickness has to be reduced whileincreasing channel-doping concentration. However, Yan, et al., “Scalingthe Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol.39, p. 1704, July 1992, have shown that to reduce short-channel effectsfor sub-0.05 μm MOSFETs, it is important to have a backside-conductinglayer present in the structure that screens the drain field away fromthe channel. The Yan, et al. results show that double-gated MOSFETs andMOSFETs with a top gate and a backside ground plane are more immune toshort-channel effects and hence can be scaled to shorter dimensions thanconventional MOSFETs.

[0004] The structure of the prior art MOSFETs consists of a very thinvertical Si layer (FIN) for the channel, with two gates, one on eachside of the channel. The two gates are electrically connected so thatthey serve to modulate the channel. Short-channel effects are greatlysuppressed in such a structure because the two gates very effectivelyterminate the drain field line preventing the drain potential from beingfelt at the source end of the channel. Consequently, the variation ofthe threshold voltage with drain voltage and with gate length of a priorart double-gated MOSFET is much smaller than that of a conventionalsingle-gated structure of the same channel length.

[0005] FIN MOSFETs offer potential benefits in performance as comparedwith conventional MOSFETs; See, for example, X. Huang, et al., IEDMTech. Dig. 1999, p.67. However, in prior art FIN MOSFETs, the gateconductor is not self-aligned to the source/drain diffusion junctions orthe channel regions. Therefore, there will be a large series resistancebetween the channel and the heavily doped source/drain diffusionjunctions.

[0006] To date, there are no adequate means for fabricating double-gatedFIN MOSFET structures in which the gate is self-aligned to thesource/drain diffusion junctions and the channels. Thus, there is acontinued need for developing a new and improved method of fabricatingdouble-gated FIN MOSFETs in which such self-alignment between the gateand the source/drain diffusion junctions and channels is achieved.

SUMMARY OF THE INVENTION

[0007] One object of the present invention is to provide adouble-gated/double-channel FIN MOSFET structure that has sub-0.05 μmchannel lengths associated therewith.

[0008] Another object of the present invention is to provide a FINMOSFET structure that has excellent short-channel characteristics.

[0009] A further object of the present invention is to provide a FINMOSFET structure in which the variation in threshold voltage with drainvoltage and with the gate length is substantially less than that of asingled-gated MOSFET structure of the same channel length.

[0010] A yet further object of the present invention is to provide a FINMOSFET structure which has double the on-current as compared withconventional single-gated structures of the same channel length.

[0011] A still further object of the present invention is to provide aFIN MOSFET structure in which the gate is self-aligned to thesource/drain diffusion junctions and channel regions therebysignificantly reducing the series resistance between the channels andthe heavily doped source/drain diffusion junctions.

[0012] These and other objects and advantages are achieved in thepresent invention by utilizing a method wherein a trough is employed,not only to define the regions where the channels are formed, but alsoto form a damascene gate. Such a method allows for the formation of adouble-gated/double-channel FIN MOSFET structure in which the gate isself-aligned to the channel regions and the source/drain diffusionjunctions.

[0013] One aspect of the present invention thus relates to a method offabricating a double-gated/double-channel FIN MOSFET structure having agate region that is self-aligned with the source/drain diffusionjunctions and channel regions. Specifically, the method of the presentinvention comprises the steps of:

[0014] (a) forming at least one patterned region atop a surface of aninsulating region, said at least one patterned region comprising aSi-containing layer present atop said insulating region, a pad oxidepresent atop said Si-containing layer and a polish stop layer presentatop said pad oxide;

[0015] (b) forming planarizing insulating regions abutting eachpatterned region, said planarizing insulating regions are formed onexposed portions of said insulating region, said planarizing insulatingregion being co-planar with a top surface of said polish stop layer;

[0016] (c) forming a hardmask on a portion of said at least onepatterned region, said hardmask being used to define channel regions insaid at least one patterned region;

[0017] (d) selectively removing a portion of said hardmask, said polishstop layer and said pad oxide layer so as to expose a portion of saidSi-containing layer thereby forming channels regions and a trough;

[0018] (e) forming a gate region in said trough; and

[0019] (f) removing said polish stop layer and said pad oxide abuttingsaid gate region so as to expose portions of said Si-containing layerand forming source/drain diffusion regions therein.

[0020] Another aspect of the present invention relates to adouble-gated/double-channel FIN MOSFET structure which is formedutilizing the method of the present invention. Specifically, theinventive double-gated/double-channel FIN MOSFET comprises:

[0021] a bottom Si-containing layer;

[0022] an insulating region present atop said bottom Si-containinglayer, said insulating region having at least one partial openingtherein;

[0023] a gate region formed in said at least one partial opening, saidgate region comprising two regions of gate conductor that are separatedfrom channel regions by an insulating film, said insulating film havingopposite vertical surfaces adjacent to the channel regions;

[0024] source/drain diffusion regions abutting said gate region, saidsource/drain diffusion regions having junctions that are self-aligned tothe channels regions as well as the gate region; and

[0025] insulating spacers that separate the gate region and thesource/drain diffusion regions formed orthogonal to said insulatingfilm.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIGS. 1-11 are pictorial representations (through cross-sectionaland, in some instances, top views) showing the inventivedouble-gated/double-channel FIN MOSFET structure through variousprocessing steps of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0027] The present invention, which provides a method of fabricating aFIN MOSFET structure having a gate region that is self-aligned with thesource/drain diffusion junctions and channel regions as well as the FINMOSFET structure itself, will now be described in greater detail byreferring to the drawings that accompany the present application. It isnoted that in the accompanying drawings, like and/or correspondingelements are referred to by like reference numerals.

[0028] Reference is first made to FIG. 1 which illustrates an initialstructure that is employed in the present invention in fabricating theinventive FIN MOSFET structure. Specifically, the initial structureshown in FIG. 1 comprises silicon-on-insulating (SOI) material 10 whichincludes bottom Si-containing layer 12, insulating region 14, and topSi-containing layer 16. Note that the insulating region, i.e., buriedoxide region, electrically isolates the bottom Si-containing layer fromthe top Si-containing layer. The term “Si-containing layer” as usedherein denotes a semiconducting material that includes at least Si.Examples of such semiconducting materials, include, but are not limitedto: Si, SiGe, SiGeC, SiC, polysilicon (i.e., polySi), epitaxial silicon(i.e., epi-Si), amorphous silicon (i.e., a:Si), and multilayers thereof.In one embodiment of the present invention, it is highly preferred thatlayers 12 and 14 of SOI material 10 are both composed of Si orpolysilicon.

[0029] The thickness of top Si-containing layer 16 of SOI material 10may vary, but typically, the Si-containing layer has a thickness of fromabout 10 to about 500 nm, with a thickness of from about 50 to about 150nm being more highly preferred. Insofar as insulating region 14 isconcerned, the insulating region typically has a thickness of from about10 to about 1000 nm, with a thickness of from about 100 to about 500 nmbeing more highly preferred. The thickness of bottom Si-containing layer12 of SOI material 10 is inconsequential to the present invention.

[0030] The SOI material shown in FIG. 1 may be made from a conventionalprocess well known in the art. For example, the SOI material may befabricated using a thermal bonding and cutting process, oralternatively, the SOI material is fabricated using a separation by ionimplantation of oxygen (SIMOX) process.

[0031]FIG. 2 illustrates the structure that is obtained after forminginsulating stack 18 atop Si-containing layer 16. As shown, insulatingstack 18 includes at least pad oxide layer 20 which is formed atopSi-containing layer 16 of the SOI material, and polish stop layer 22which is composed of an insulating layer that has a different etch rateas compared to that of the underlying pad oxide layer. For example, thepolish stop layer may be composed of a nitride such as SiN, or anoxynitride such as SiON, when the pad oxide is formed of SiO₂.

[0032] Pad oxide layer 20 of insulating stack 18 is formed utilizing aconventional deposition process such as chemical vapor deposition (CVD),plasma-assisted CVD, sputtering, evaporation, chemical solutiondeposition, or atomic layer deposition. Alternatively, and morepreferably, pad oxide layer 20 is formed utilizing a conventionalthermal oxidation process. The thickness of the pad oxide layer may varydepending on the type of oxide employed as well as the process used informing the same. Typically, however, pad oxide layer 20 has a thicknessof from about 5 to about 200 nm, with a thickness of from about 10 toabout 50 nm being more highly preferred.

[0033] The polish stop layer, which is formed utilizing a conventionaldeposition process including low-pressure CVD, has a thickness of fromabout 50 to about 500 nm, with a thickness of from about 100 to about200 nm being more highly preferred. It is noted that the thickness ofthe polish stop layer may vary somewhat from the ranges reported herein.

[0034] Next, and as shown in FIG. 3, at least one patterned region 24,which is comprised of patterned layers 22, 20 and 16, is formedutilizing conventional lithography and etching. The lithography stepemployed in forming the at least one patterned region includes the stepsof forming a photoresist atop polish stop layer 22; exposing thephotoresist to a pattern of radiation; and developing the pattern in thephotoresist utilizing a conventional resist developer. The etching stepemployed in forming patterned region 24 comprises a conventional dryetching process such as reactive-ion etching (RIE), ion beam etching(IBE), plasma etching, laser ablation or any combination thereof whichis capable of removing exposed regions of layers 22, 20 and 16, whilestopping on insulating region 14.

[0035] Following the etching process, the patterned resist is removedproviding the structure shown in FIG. 3. Note that patterned region 24defines the active area, See FIG. 4B, of the inventive structure. It isalso noted that although the drawings depict the formation of only onepatterned region, the present invention contemplates forming a pluralityof such patterned regions on the structure.

[0036] FIGS. 4A(cross-sectional view)-4B (top view) show the structurethat is obtained after planarizing isolation regions 26 are formedabutting patterned region 24. The planarizing isolation regions areformed by first depositing, via conventional deposition processes suchas low-pressure CVD, an oxide layer such as SiO₂ over all exposedsurfaces of the structure shown in FIG. 3, and thereafter planarizingthe deposited oxide layer down to the top surface of polish stop layer22 utilizing a conventional planarization process such aschemical-mechanical polishing (CMP) or grinding.

[0037] Patterned hardmask 28 is then formed atop the uppermost layer ofpatterned region 24, i.e., atop polish stop layer 22, utilizing aconventional deposition process such as low-pressure CVD, followed byconventional lithography and etching. The resultant structure obtainedafter these steps of the present invention is shown, for example, inFIG. 5.

[0038] Patterned hardmask 28 has a width of about 50 nm or less, with awidth of from about 5 to about 50 nm being more highly preferred. Thevertical thickness of the patterned hardmask is typically of from about50 to about 500 nm, with a vertical thickness of from about 100 to about200 nm being more highly preferred. Note that the patterned hardmask maybe composed of the same or different oxide as planarizing insulatingregions 26 and that the patterned hardmask is employed in the presentinvention in defining channel regions 35.

[0039] Next, and as illustrated in FIGS. 6A (cross-sectional)-6B (topview), patterned photoresist 30 having at least one opening 32 exposinga portion of patterned hardmask 28 is then formed over the structureshown in FIG. 5. Specifically, patterned resist 30 having opening 32 isformed utilizing conventional lithography as described hereinabove. Itis noted that this step of the present invention defines the regionswhere the gate conductor will be subsequently formed. At this point ofthe present invention, any polish stop layer that is adjacent to thechannel region, not protected by patterned hardmask 28, is removedutilizing a selective RIE process.

[0040] To define the structure shown in FIGS. 6A-6B, that structure issubjected to selective etching processes that are capable of removingthe exposed portions of patterned hardmask 28 as well as the underlyingportions of polish stop layer 22 stopping on a portion of pad oxidelayer 20. The resulting structure formed after these selective etchingprocesses is shown, for example, in FIGS. 6A (cross-sectional)-6B (topview). The selective etching processes used at this point of the presentinvention include the use of a first etching process that selectivelyremoves oxide as compared to nitride, and a second etching process whichselectively removes nitride as compared to oxide.

[0041] The first etching process may comprise the use of afluorine-containing gas or plasma having an etch selectivity of at leastabout 20:1, whereas the second etching process may include the use ofCl-based chemistries having an etch selectivity of at least about 10:1.Note that the second etching process defines channel regions 35 of theinventive structure.

[0042] FIGS. 7A-7B show the resultant structure after conducting theselective etching processes which provide troughs 34 in the isolationregions for the gate conductors. The etch is a fluorine-base chemistrythat etches SiO₂ selective to Si₃N₄.

[0043] This selective etching processes also removes the exposedportions of pad oxide 20 from the regions adjacent to the channel (i.e.,those regions not protected by hardmask 22). See, for example, in FIG.7B. The structure shown in FIG. 8 is obtained by utilizing a thirdselective etching process in which a chlorine-containing etching gas orplasma having an etch selectivity of at least about 10:1 is employed.This etches the exposed Si adjacent to hardmask 22, leaving a verticalSi FIN that defines the channel regions. Following the third selectiveetching process, the resist is removed utilizing a conventionalstripping process well known to those skilled in the art. Note thatportions of hardmask 28 are also removed at this point of the presentinvention.

[0044] After stripping the resist from the structure, a sacrificialoxide layer (not shown) is formed by conventional thermal growingprocesses on the exposed wall portions of the trough, the sacrificialoxide is thereafter removed using a chemical etchant such as HF, and anoxide layer (not shown) is then formed on the exposed, and now cleaned,tough sidewalls.

[0045] FIGS. 9A(cross-section)-9B(top view) show the resultant structurethat is obtained after insulating spacers 36 and gate dielectric 38 areformed in the trough. Specifically, the insulating spacers are formedutilizing a conventional deposition process such as low-pressure CVD andetching, e.g., RIE wherein a fluorine-based plasma is employed. Notethat over-etching is typically employed so as to remove spacers from thechannel regions. The thickness of hardmask 22 should be greater than thethickness of Si layer 16 so that spacers remain adjacent to thesource/drain diffusion regions, but not on the channel regions.Insulating spacers 36 are comprised of an oxide, a nitride, anoxynitride or any combination and multilayer thereof.

[0046] Next, a sacrificial oxide layer (not shown) is formed, asdescribed above, then the sacrificial oxide layer is removed, asdescribed above, and thereafter gate dielectric 38 is formed byutilizing a conventional deposition process. Alternatively, aconventional thermal growing process may be used in forming the gatedielectric.

[0047] The gate dielectric formed at this point of the present inventionmay include an oxide, a nitride, an oxynitride or any combinationthereof including multilayers. A preferred gate dielectric employed inthe present invention is an oxynitride such as SiON.

[0048] The thickness of the gate dielectric formed at this point of thepresent invention may vary depending on the gate dielectric material aswell as the process used in forming the same. Typically, gate dielectric38 has an effective electrical thickness assuming the dielectricconstant is equal to that of SiO₂ of from about 1 to about 5 nm, with athickness of from about 1 to about 2 nm being more highly preferred.

[0049] Following the formation of the insulating spacers and gatedielectric, gate conductor 40 is formed over the channel and the troughregions shown in FIGS. 9A-9B. The resultant structure after formation ofgate conductor 40 is shown in FIG. 10. Note that the top surface of thegate conductive material is co-planar with the top surface of isolationregions 26. Specifically, the gate conductor material is depositedutilizing a conventional deposition process including low-pressure CVDand thereafter a conventional planarization process such as CMP isemployed.

[0050] The gate conductor material used at this point of the presentinvention includes any conductive material which is typically employedin MOSFET devices. For example, the gate conductive material employed inthe present invention may be comprised of polysilicon, amorphous Si,elemental metals that are conductive, alloys of conductive elementalmetals, silicides or nitrides of conductive elemental metals andmultilayers thereof, e.g., a conductive gate stack including, forexample, a layer of polysilicon and a conductive elemental metal. When aconductive gate stack is employed, a conventional diffusion barrier suchas Ta, Ti, TaN or TiN may be formed between the conductive layers.

[0051] Polish stop layer 22 and pad oxide layer 20 are then removed fromthe structure utilizing conventional wet etching processes or a chemicaldown stream dry etching process well known in the art so as to exposeportions of underlying Si-containing layer 16. The exposed portions ofthe Si-containing layer are then subjecting to a ion implantationprocess wherein an ion (n- or p-type) is implanted using an ion dose onthe order of about 1E15 atoms/cm² or greater. Following ionimplantation, the doped regions of the Si-containing layer are annealedat a temperature of about 700° C. or greater so as to form activatedsource/drain diffusion regions 42 that have junction regions which areself-aligned to the gate edges.

[0052] The resultant structure obtained using the inventive process isshown, for example, in FIG. 11A (cross-sectional) and B (top view).Specifically, the inventive structure includes bottom Si-containinglayer 12, an insulating region (14 and 26) present atop the bottomSi-containing layer. Insulating region (14+26) having at least onepartial opening 50 therein. A gate region 70 formed in the partialopening, said gate region comprising two regions of gate conductor 40that are separated from channel regions 35 by insulating film, i.e.,gate dielectric, 38 which surrounds a portion of Si-containing layer 16,said insulating film having opposite vertical surfaces adjacent tochannel regions 35; source/drain diffusion regions 42 abutting said gateregion, said source/drain diffusion regions having junctions that areself-aligned to the channels regions as well as the gate region; andinsulating spacers 36 that separate gate region 70 and source/draindiffusion regions 42 formed orthogonal to insulating film 38.

[0053] In addition to the processing steps mentioned above, the presentinvention also contemplates other conventional MOSFET processing stepsthat are well known in the art. For example, the present invention alsocontemplates forming salicide regions atop the source/drain diffusionregions, and forming contacts and/or interconnects over the salicideregions.

[0054] While the present invention has been particularly shown anddescribed with respect to preferred embodiments thereof, it will beunderstood by those skilled in the art that the foregoing and otherchanges in forms and details may be made without departing from thescope and spirit of the present invention. It is therefore intended thatthe present invention not be limited to the exact forms and detailsdescribed and illustrated, but fall within the scope of the appendedclaims.

Having thus described our invention in detail, what we claim as new anddesire to secure by the Letters Patent is:
 1. A method of fabricating athin vertical channel (FIN) metal oxide semiconductor field effecttransistor (MOSFET) comprising the steps of: (a) forming at least onepatterned region atop a surface of an insulating region, said at leastone patterned region comprising a Si-containing layer present atop saidinsulating region, a pad oxide present atop said Si-containing layer anda polish stop layer present atop said pad oxide; (b) forming planarizinginsulating regions abutting each patterned region, said planarizinginsulating regions are formed on exposed portions of said insulatingregion, said planarizing insulating region being co-planar with a topsurface of said polish stop layer; (c) forming a hardmask on a portionof said at least one patterned region, said hardmask being used todefine channel regions in said at least one patterned region; (d)selectively removing a portion of said hardmask, said polish stop layerand said pad oxide layer so as to expose a portion of said Si-containinglayer thereby forming channels regions and a trough; (e) forming a gateregion in said trough; and (f) removing said polish stop layer and saidpad oxide abutting said gate region so as to expose portions of saidSi-containing layer and forming source/drain diffusion regions therein.2. The method of claim 1 wherein said Si-containing layer and saidinsulating region are components of a silicon-on-insulating (SOI)material.
 3. The method of claim 1 wherein step (a) comprisingdeposition, lithography and etching.
 4. The method of claim 1 whereinsaid planarizing insulating regions are formed by deposition andplanarization.
 5. The method of claim 1 wherein said hardmask is formedby deposition of an oxide and patterning.
 6. The method of claim 1wherein step (d) comprising a series of etching processes whereinvarious etchant gases or plasma are employed to selectively removedesired layers.
 7. The method of claim 1 wherein said gate regionincludes a gate dielectric, a gate conductor and insulating spacers. 8.The method of claim 7 wherein said gate dielectric is formed bydeposition or a thermal growing process.
 9. The method of claim 7wherein said gate conductor is formed by deposition and planarization.10. The method of claim 7 wherein said gate conductor is comprised ofpolysilicon, amorphous silicon, a conductive elemental metal, a nitrideor silicide of a conductive elemental metal, an alloy of a conductiveelemental metal or multilayers thereof.
 11. The method of claim 7wherein said insulating spacers are formed by deposition and etching.12. The method of claim 1 wherein said source/drain diffusion regionsare formed by ion implantation and activation annealing.
 13. A thin filminsulating (FIN) metal oxide semiconductor field effect transistor(MOSFET) comprising: a bottom Si-containing layer; an insulating regionpresent atop said bottom Si-containing layer, said insulating regionhaving at least one partial opening therein; a gate region formed insaid partial opening, said gate region comprising two regions of gateconductor that are separated from channel regions by an insulating film,said insulating film having opposite vertical surfaces adjacent to thechannel regions; source/drain diffusion regions abutting said gateregion, said source/drain diffusion regions having junctions that areself-aligned to the channels regions as well as the gate region; andinsulating spacers that separate the gate region and the source/draindiffusion region formed orthogonal to said insulating film.
 14. The FINMOSFET of claim 13 wherein said insulating region includes an insulatinglayer of an SOI material.
 15. The FIN MOSFET of claim 13 wherein saidpartial opening exposes a portion of said insulating layer of said SOImaterial.
 16. The FIN MOSFET of claim 13 wherein said insulating film isformed surrounding a portion of a Si-containing layer, said insulatingfilm is comprised of a gate dielectric.
 17. The FIN MOSFET of claim 16wherein said gate dielectric is comprised of an oxide, a nitride, anoxynitride or any combination or multilayer thereof.
 18. The FIN MOSFETof claim 13 wherein said regions of gate conductor are each comprised ofpolysilicon, amorphous Si, a conductive elemental metal, an alloy of aconductive elemental metal, a nitride or silicide of a conductiveelemental metal or multilayers thereof.
 19. The FIN MOSFET of claim 13further comprising salicide regions formed atop said source/draindiffusion regions.
 20. The FIN MOSFET of claim 13 wherein saidsource/drain diffusion regions are formed in a portion of a patternedSi-containing layer.